1. Field
The present application relates to a semiconductor device and a method for controlling the semiconductor device.
2. Description of the Related Art
In Japanese Unexamined Patent Application Publication No. 2000-258505, a typical direct-current (DC)-test circuit is discussed which performs a DC test (an electric characteristics test) that is performed when a multiple-pin large scale integrated circuit (LSI) chip is to be shipped. The typical DC-test circuit includes the following elements: means for simultaneously inputting the same expected-value signals to a plurality of output buffers of an LSI chip; means for comparing output signals of the output buffers to a reference value to obtain a comparison result; means for generating one signal that can detect even one malfunctioned output buffer among many output buffers from the comparison result; and means for outputting the generated signal to an LSI tester from one terminal. The LSI tester detects whether or not the DC test has been normally performed by comparing input signals to a test signal.
In a typical DC test circuit, one signal is generated based on the comparison-result signal obtained by comparing the output signals of the output buffers to the reference value, when even one malfunctioning output buffer exists among the output buffers, indicating that the malfunctioned output buffer is detected. The one signal is output to the LSI tester, and the LSI tester detects whether the DC test has been normally or abnormally performed. Regardless of the number of pins, such as output pins of the LSI chip, the LSI tester performs the DC test using at least one monitor pin.
In Japanese Unexamined Patent Application Publications No. 2001-15684 and No. 2004-88641, technologies for performing operation tests on semiconductor circuits are discussed.